A Layered Architecture for Accelerating Matrix Computations

Many scientific and engineering applications are naturally expressed in terms of dense matrix or vector algorithms. This paper presents an FGPA-based matrix acceleration engine that improves the performance of dense matrix and vector algorithms. The engine offloads common data management tasks normally performed by processing resources onto a dedicated sequencer. The sequencer adopts an event-based parameter update mechanism to give it the flexibility to accelerate a wide range of matrix algorithms. An implementation of the sequencer has been developed and tested on a Xilinx Virtex-5LX FPGA. This implementation uses 1856 slices and has an operating speed of 64 MHz, making it comparable to the OpenRISC CPU core to which it attaches.